Overview

In this project, we explore novel microarchitectures on multi-core substrates and novel microarchitecture mechanisms for accelerating single-thread performance. The theme is to accelerate computation that iterates over a program's objects and also react to changes in these objects before they are revisited.

Publications

Conference and Journal Papers

M. Al-Otoom, E. Forbes, and E. Rotenberg. EXACT: Explicit Dynamic-Branch Prediction with Active Updates. Proceedings of the 7th ACM International Conference on Computing Frontiers (CF-7), pp. 165-176, May 2010. [pdf]

Workshop Papers

M. Al-Otoom, R. Sheikh, and E. Rotenberg. A Case for a Software-Managed Reconfigurable Branch Predictor. 5th Workshop on Architectural and Microarchitectural Support for Binary Translation (AMAS-BT'12), in conjunction with ISCA-39, June 2012. [pdf]

Technical Reports

M. Dechene, J. E. Forbes, and E. Rotenberg. Multithreaded Instruction Sharing. Technical Report, Department of Electrical and Computer Engineering, North Carolina State University, December 2010. [pdf]

Student Theses

M. M. Al-Otoom. EXACT: Explicit Dynamic-Branch Prediction with Active Updates. Ph.D. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, August 2010. [NCSU library: on-line thesis]

Talks

EXACT: Explicit Dynamic-Branch Prediction with Active Updates. Presented at CF-7 by E. Rotenberg. [pps]

Funding

This project is supported by NSF grants CCF-0702632 (The Phase Based Behavior of Objects) and CCF-0916481 (SHF:Small: EXACT: Explicit Dynamic-Branch Prediction with Active Updates), SRC grant 2007-HJ-1594, and an Intel gift.

Any opinions, findings, and conclusions or recommendations expressed in this website and publications herein are those of the author(s) and do not necessarily reflect the views of the National Science Foundation.