Welcome to my new web page. This page will continue to host the benchmarks from the 1990's that used to reside under http://www.cbl.ncsu.edu. If you are browsing for these benchmarks, please proceed by clicking here. I have worked for nearly 20-years in industry while also affiliated with a number of universities in Canada, North Carolina, Germany, Slovenia, Saudi Arabia, and Brazil. In 1986 I initiated, then continued as a General Chair until 1992, the International ACM Workshop Series on Layout and Logic Synthesis, held yearly at MCNC, Research Triangle Park, NC (with about 150 attendees from Americas, Europe, and Asia). This trend-setting series of workshops was a follow-up on the innovative organization of IEEE special sessions at ISCAS85 (Kyoto, Japan) and at ISCAS89 (Seattle, WA); both sessions were associated with distributions of challenging test generation benchmarks, now known under these acronyms. There are still some 40,000 search engine hits for each of these two acronyms alone. A world-wide following from other special interest groups, including the NSF-sponsored DIMACS series of workshops, ensued.
Since 2000, I have been actively engaged in promoting a more disciplined approach to performance testing of combinatorial algorithms. Particularly, the use of graph isomorphs did expose large performance runtime variability of competing algorithms and thereby did enable rigorous statistical runtime performance testing of the underlying solvers. Our experiments with hard combinatorial problems in different domains continue to demonstrate the intrinsic merits of a statistical model that reliably predicts the asymptotic runtime complexity of any solver -- provided that the solver is tested, without censoring, on a well-defined family of instances of increasing size. For details, click on Publications header above.
CV/Resume2-page CV (pdf)
Ph.D. 1970 Electrical Engineering, University of Colorado, Boulder, Colorado, USA
Dipl.-Ing. 1965 Electrical Engineering, University of Ljubljana, Slovenia
- 1995-2000: Two grants by DARPA ($1,000,000), Globally Distributed Microsystems Design: Proof-of-Concept (The Vela Project). This collaborative project engaged 6 universities: see the 1998 IEEEE Spectrum article, and summaries of demos at 1998/1999/2000 Design Automation Conferences
- 1994-1998: Grants by SRC/Sematech ($400,000) National Benchmark Program in Microelectronic Systems Design Automation
- 1992-1994: Grants by ACM/SIGDA ($84,000), Benchmark Archival and Distribution
- 1992: Grant by Siemens Corp. ($62,000), Partitioning and Testability of FPGAs
- 1992: Travel and Scholarship Grant by German Science Foundation, a collaborative research sabbatical at the Technical University of Munich, Germany
- 1991: Travel Grant by Saudi Arabian Ministry of Education for a short course on CAD methods for VLSI design at at King Fahd University, and an invited talk at VLSI conference in Dhahran, Saudi Arabia
- 1990: Best paper award, IEEE International Conference on Circuits, Computers, and Design
- 1990: Travel Grant by Brazilian Engineering Society for a short course on CAD methods for VLSI design at University of Sao Paulo, and an invited talk at VLSI conference in Porto Allegre, Brazil
- 1966: Dr. France Preseren's Award for best Diploma Thesis in Electrical Engineering, University of Ljubljana, Slovenia