Post-Silicon Microarchitecture
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Overview

Achieving large gains in single-thread performance (e.g., 2x, as opposed to 2%-5% per new feature) seems impossible without a paradigm shift in microarchitecture. This project explores Post-Silicon Microarchitecture (PSM). The key idea is to tightly couple a best-in-class general-purpose superscalar core with a reconfigurable logic fabric, PSM-RF. Here's what is fundamentally different between PSM and past works coupling cores with reconfigurable logic. A flexible and efficient interface, PSM-A (short for PSM Agent), allows for PSM-RF to observe and microarchitecturally intervene at key pipeline stages of the superscalar core. New microarchitectural components are synthesized on-demand to PSM-RF. Instructions still flow through the pipeline, as usual, but their execution is streamlined (better instructions per cycle (IPC)) through microarchitectural intervention by PSM-RF. Our research shows that one can achieve unprecedented speedups of individual applications, by analyzing their bottlenecks and providing customized microarchitectural solutions to target these bottlenecks. Examples of PSM use-cases are: application-customized branch predictors; application-customized data prefetchers; deploying and retooling (sometimes with special adjustments per-application) previously-proposed exotic microarchitecture ideas, where PSM changes the value proposition in favor of their commercialization.


Publications

Conference and Journal Papers

C. Kumar, A. Seshadri, A. Chaudhary, S. Bhawalkar, R. Singh, and E. Rotenberg. Post-Fabrication Microarchitecture. Proceedings of the 54th IEEE/ACM International Symposium on Microarchitecture (MICRO-54), pp. ?-?, October 2021. (to appear) [pdf]

C. Kumar, A. Chaudhary, S. Bhawalkar, U. Mathur, S. Jain, A. Vastrad, and E. Rotenberg. Post-Silicon Microarchitecture. IEEE Computer Architecture Letters (CAL), 19(1):26-29, Jan.-June 1, 2020. (Date of Publication: 09 March 2020.) [pdf]
Awards:

  • 2020 Best of CAL, for the paper "Post-Silicon Microarchitecture" (2021)
    Awarded to the top three papers published in IEEE Computer Architecture Letters in a given year. Authors present at HPCA's "Best of CAL" session.
  • IEEE Computer "Spotlight on Transactions", for the paper "Post-Silicon Microarchitecture" (2021)
    Editor in Chief of IEEE Computer Architecture Letters publishes a spotlight article in IEEE Computer, describing the highest rated CAL paper in the previous year.

Student Theses

S. Bhawalkar. Custom Data Prefetchers Evaluated on a Post-Silicon-Microarchitecture-Enabled Superscalar Processor. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, July 2020. [NCSU library: on-line thesis]

C. Kumar. Post-Silicon Microarchitecture. Ph.D. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, May 2020. [NCSU library: on-line thesis]

A. Vastrad. Verilog Design and Verification of an Application Specific Branch Predictor for astar Benchmark. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, May 2019. [NCSU library: on-line thesis]

S. Jain. Application Specific Parallelization. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, March 2019. [NCSU library: on-line thesis]

A. Chaudhary. Custom EXACT Branch Predictor for astar Benchmark. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, March 2019. [NCSU library: on-line thesis]

U. Mathur. Post-Silicon Microarchitecture (PSM) Implementation of Checkpointed Early Load Retirement (CLEAR). M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, March 2019. [NCSU library: on-line thesis]


Talks


Funding

This project is funded by the NSF/Intel Partnership on Foundational Microarchitecture Research (FoMR) (NSF grant no. CCF-1823517 and matching Intel grant) and other Intel grants.

Any opinions, findings, and conclusions or recommendations expressed in this website and publications herein are those of the author(s) and do not necessarily reflect the views of the National Science Foundation or Intel Corporation.